mux.vhdl

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library ieee;
    use ieee.std_logic_1164.all;
 
 
entity mux_using_with is
    port (
        din_0   : in  std_logic;
        din_1   : in  std_logic;
        sel     : in  std_logic;
        mux_out : out std_logic
    );
end entity;
 
architecture behavior of mux_using_with is
begin
    with (sel) select
    mux_out <= din_0 when '0',
               din_1 when others;
end architecture;